1. Field of the Invention
Embodiments of the present disclosure relate to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices including capacitors and metal contacts and methods of fabricating the same.
2. Description of the Related Art
Dynamic random access (DRAM) devices employ cell capacitors as data storage elements. A height of cell capacitors has been increased to obtain large cell capacitance in a limited cell array area without degradation of the integration density of the DRAM devices. Cylinder-shaped storage nodes have been widely employed to increase the height of the cell capacitors. The storage nodes may be formed in through holes penetrating a mold layer. However, as a design rule of the DRAM devices reduces, an aspect ratio of the through holes has been increased. Thus, when the height of the cell capacitors increases, it may be difficult to form the through holes completely passing through the mold layer using an etching process. That is, there may be some limitations in forming through holes having a high aspect ratio.
Further, if the height of the storage nodes in a cell array region increases, a height of metal contact holes formed in a peripheral circuit region or a core region may also increase. That is, an aspect ratio of the metal contact holes may also increase. Accordingly, even though an insulation layer is over-etched to form the metal contact holes, the metal contact holes cannot expose underlying conductive patterns. This is due to polymer generated during the etching process for forming the metal contact holes. More specifically, the metal contact holes may be formed to have a sloped sidewall profile because of the polymer. Finally, the metal contact holes may not completely penetrate the mold layer even though the etch time increases. Therefore, the polymer generated during the etching process may cause a process failure in that the metal contact holes do not expose the underlying conductive patterns. This process failure may be referred to hereinafter as “an open fail.”
Moreover, when the metal contact holes are misaligned with the underlying conductive patterns, an insulation layer adjacent to the underlying conductive patterns may also be etched to expose undesired conductive patterns during an over etching step of the etching process for forming the metal contact holes. This is because etching time is increased in proportion to the height of the metal contact holes, and thus the over etching time is also increased in proportion of the height of the metal contact holes.
Furthermore, if the aspect ratio of the metal contact holes increases, it may be difficult to fill the metal contact holes with a conductive layer such as a metal layer without any voids therein.